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general description the MAX1438B octal, 12-bit analog-to-digital converter (adc) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. this adc is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. the MAX1438B operates from a 1.8v sin- gle supply and consumes only 913mw (114mw per channel) while delivering a 69.9db (typ) signal-to-noise ratio (snr) at a 5.3mhz input frequency. in addition to low operating power, the MAX1438B features a low- power standby mode for idle periods. an internal 1.24v precision bandgap reference sets the full-scale range of the adc. a flexible reference struc- ture allows the use of an external reference for applica- tions requiring increased accuracy or a different input voltage range. the reference architecture is optimized for low noise. a single-ended clock controls the data-conversion process. an internal duty-cycle equalizer compensates for wide variations in clock duty cycle. an on-chip phase-locked loop (pll) generates the high-speed ser- ial low-voltage differential signal (lvds) clock. the MAX1438B has self-aligned serial lvds outputs for data, clock, and frame-alignment signals. the output data is presented in twos-complement format. the MAX1438B offers a maximum sample rate of 64msps. this device is available in a small, 10mm x 10mm x 0.8mm, 68-pin thin qfn package with exposed pad and is specified for the extended industrial (-40c to +85c) temperature range. applications ultrasound and medical imaging instrumentation multichannel communications features ? excellent dynamic performance 69.9db snr at 5.3mhz 94dbc sfdr at 5.3mhz ? ultra-low power 114mw per channel (normal operation) ? serial lvds outputs ? pin-selectable lvds/slvs (scalable low-voltage signal) mode ? lvds outputs support up to 30in fr4 backplane connections ? test mode for digital signal integrity ? fully differential analog inputs ? wide differential input voltage range (1.4v p-p ) ? on-chip 1.24v precision bandgap reference ? clock duty-cycle equalizer ? compact, 68-pin thin qfn package with exposed pad ? evaluation kit available (order max1437bevkit) MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs ________________________________________________________________ maxim integrated products 1 ordering information 19-4630; rev 0; 7/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. evaluation kit available part temp range pin-package MAX1438Betk+ -40c to +85c 68 thin qfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad.
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to gnd........................................................-0.3v to +2.0v cvdd to gnd........................................................-0.3v to +3.6v ovdd to gnd .......................................................-0.3v to +2.0v in_p, in_n to gnd .................................-0.3v to (v avdd + 0.3v) clk to gnd ...........................................-0.3v to (v cvdd + 0.3v) out_p, out_n, frame_, clkout_ to gnd ..............................-0.3v to (v ovdd + 0.3v) dt, slvs/ lvds , lvdstest, pll_, stby refio, refadj, cmout to gnd......-0.3v to (v avdd + 0.3v) continuous power dissipation (t a = +70c) 68-pin thin qfn, 10mm x 10mm x 0.8mm (derate 70mw/c above +70c) ................................4000mw operating temperature range ...........................-40c to +85c maximum junction temperature .....................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c electrical characteristics (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v, external v refio = 1.24v, c refio to gnd = 0.1f || 1.0f, c refp to gnd = 10f, c refn to gnd = 10f, f clk = 64mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units dc accuracy (note 2) resolution n 12 bits integral nonlinearity inl 0.4 2.5 lsb differential nonlinearity dnl no missing codes over temperature 0.25 1 lsb offset error 0.5 %fs gain error -3 0.5 +2 %fs analog inputs (in_p, in_n) input differential range v id differential input 1.4 v p-p common-mode voltage range v cmo 0.76 v common-mode voltage range tolerance (note 3) 50 mv differential input impedance r in switched capacitor load 2 k ? differential input capacitance c in 12.5 pf conversion rate maximum conversion rate f smax 64 mhz minimum conversion rate f smin 4.0 mhz data latency 6.5 cycles dynamic characteristics (differential inputs, 4096-point fft) (note 2) f in = 5.3mhz at -0.5dbfs 69.9 signal-to-noise ratio snr f in = 20mhz at -0.5dbfs 67 69.6 db f in = 5.3mhz at -0.5dbfs 69.8 signal-to-noise and distortion sinad f in = 20mhz at -0.5dbfs 67 69.6 db f in = 5.3mhz at -0.5dbfs 11.4 effective number of bits enob f in = 20mhz at -0.5dbfs 10.8 11.4 bits f in = 5.3mhz at -0.5dbfs 94 spurious-free dynamic range sfdr f in = 20mhz at -0.5dbfs 79 93 dbc
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v , external v refio = 1.24v, c refio to gnd = 0.1f || 1.0f, c refp to gnd = 10f, c refn to gnd = 10f, f clk = 64mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units f in = 5.3mhz at -0.5dbfs -95 total harmonic distortion thd f in = 20mhz at -0.5dbfs -92 -79 dbc intermodulation distortion imd f 1 = 5.3mhz at -6.5dbfs f 2 = 6.3mhz at -6.5dbfs 89.3 dbc third-order intermodulation im3 f 1 = 5.3mhz at -6.5dbfs f 2 = 6.3mhz at -6.5dbfs 97.5 dbc aperture jitter t aj figure 10 < 0.4 ps rms aperture delay t ad figure 10 1 ns small-signal bandwidth ssbw input at -20dbfs 100 mhz full-power bandwidth lsbw input at -0.5dbfs 100 mhz output noise in_p = in_n 0.44 lsb rms overrange recovery time t or r s = 25 ? , c s = 50pf 1 clock cycle internal reference refadj internal reference-mode enable voltage (note 4) 0.1 v refadj low-leakage current 1.5 ma refio output voltage v refio 1.18 1.24 1.30 v reference temperature coefficient tc refio 120 ppm/c external reference refadj external reference- mode enable voltage (note 4) v avdd - 0.1v v refadj high-leakage current 200 a refio input voltage 1.24 v refio input voltage tolerance 5 % refio input current i refio < 1 a common-mode output (cmout) cmout output voltage v cmout 0.76 v clock input (clk) input high voltage v clkh 0.8 x v avdd v input low voltage v clkl 0.2 x v avdd v clock duty cycle 50 % clock duty-cycle tolerance 30 % input at gnd 5 input leakage di in input at v avdd 80 a input capacitance dc in 5pf
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v, external v refio = 1.24v, c refio to gnd = 0.1f || 1.0f, c refp to gnd = 10f, c refn to gnd = 10f, f clk = 64mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units digital inputs (pll_, lvdstest, dt, slvs, stby) input high threshold v ih 0.8 x v avdd v input low threshold v il 0.2 x v avdd v input at gnd 5 input leakage di in input at v avdd 80 a input capacitance dc in 5pf lvds outputs (out_p, out_n), slvs/ lvds = 0 differential output voltage v ohdiff r term = 100 ? 250 450 mv output common-mode voltage v ocm r term = 100 ? 1.125 1.375 v rise time (20% to 80%) t rl r term = 100 ? , c load = 5pf 350 ps fall time (80% to 20%) t fl r term = 100 ? , c load = 5pf 350 ps slvs outputs (out_p, out_n, clkoutp, clkoutn, framep, framen), slvs/ lvds = 1, dt = 1 differential output voltage v ohdiff r term = 100 ? 205 mv output common-mode voltage v ocm r term = 100 ? 220 mv rise time (20% to 80%) t rs r term = 100 ? , c load = 5pf 320 ps fall time (80% to 20%) t fs r term = 100 ? , c load = 5pf 320 ps standby mode (stby) stby fall to output enable t enable 200 s stby rise to output disable t disable 60 ns power requirements avdd supply voltage range v avdd 1.7 1.8 1.9 v ovdd supply voltage range v ovdd 1.7 1.8 1.9 v cvdd supply voltage range v cvdd 1.7 1.8 3.5 v stby = 0, dt = 0 422 465 stby = 0, dt = 1 422 avdd supply current i avdd f in = 20mhz at -0.5dbfs stby = 1, no cl ock i np ut 37 ma stby = 0 85 110 stby = 0, dt = 1 85 ma ovdd supply current i ovdd f in = 20mhz at -0.5dbfs stby = 1, no cl ock i np ut 16 a cvdd supply current i cvdd cvdd is used only to bias esd-protection diodes on clk input, figure 2 0ma power dissipation p diss f in = 20mhz at -0.5dbfs 913 1035 mw
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 5 electrical characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v, external v refio = 1.24v, c refio to gnd = 0.1f || 1.0f, c refp to gnd = 10f, c refn to gnd = 10f, f clk = 64mhz (50% duty cycle), dt = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units timing characteristics (note 5) data valid to clkout rise/fall t od figure 5 (note 6) (t sample /24) - 0.15 (t sample /24) + 0.15 ns clkout output-width high t ch figure 5 t s am p le /12 ns clkout output-width low t cl figure 5 t s am p le /12 ns frame rise to clkout rise t cf figure 4 (note 6) (t sample /24) - 0.15 (t sample /24) + 0.15 ns sample clk rise to frame rise t sf figure 4 (note 6) ( t s am p le /2) + 1.1 ( t s am p le /2) + 2.6 ns crosstalk (note 2) -73 db gain matching c gm f in = 5.3mhz (note 2) 0.1 db phase matching c pm f in = 5.3mhz (note 2) 0.25 d eg r ees note 1: specifications at t a +25c are guaranteed by production testing. specifications at t a < +25c are guaranteed by design and characterization and not subject to production testing. note 2: see definition in the parameter definitions section at the end of this data sheet. note 3: see the common-mode output (cmout) section. note 4: connect refadj to gnd directly to enable internal reference mode. connect refadj to avdd directly to disable the internal bandgap reference and enable external reference mode. note 5: data valid to clkout rise/fall timing is measured from 50% of data output level to 50% of clock output level. note 6: guaranteed by design and characterization. not subject to production testing. typical operating characteristics (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 64mhz (50% duty cycle), dt = 0, c load = 10pf, t a = +25c, unless otherwise noted.) fft plot (16,384-point data record) MAX1438B toc01 frequency (mhz) amplitude (dbfs) 0 -100 -110 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 510152025 30 hd2 hd3 f clk = 64.0000006mhz f in = 5.3164063mhz a in = -0.5dbfs snr = 69.881db sinad = 69.874db thd = -101.811db sfdr = 100.723db fft plot (16,384-point data record) frequency (mhz) amplitude (dbfs) MAX1438B toc02 0 -100 -110 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 510152025 30 hd2 hd3 f clk = 64.0000001mhz f in = 30.3007813mhz a in = -0.5dbfs snr = 69.609db sinad = 69.585db thd = -92.323dbc sfdr = -92.870dbc crosstalk (16,384-point data record) frequency (mhz) amplitude (dbfs) MAX1438B toc03 0 -100 -110 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 510152025 30 f in(n2) measured on channel 1, with interfering signal on channel 2 f in(n1) = 5.3164063mhz f in(n2) = 30.3007813mhz crosstalk = -72.5db
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 64mhz (50% duty cycle), dt = 0, c load = 10pf, t a = +25c, unless otherwise noted.) m ax1438b toc04 frequency ( m hz) a m plitude (dbfs) 0 -10 -20 -30 -40 -50 -70 -60 -80 -100 -90 -110 two-tone intermodulation distortion (16,384-point data record) f in(in1) = 5 . 296593 m hz f in(in2) = 6 . 299991 m hz a in1 = -6 . 5dbfs a in2 = -6 . 5dbfs i m d = 89 . 3dbc i m 3 = 97 . 5dbc 0 5 10 15 20 25 30 bandwidth vs. analog input frequency analog input frequency (mhz) gain (db) 100 10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 -10 1 1000 MAX1438B toc05 full-power bandwidth -0.5dbfs small-signal bandwidth -20.5dbfs signal-to-noise ratio vs. analog input frequency f in (mhz) snr (db) 100 80 60 40 20 66 67 68 69 70 71 72 65 0 120 MAX1438B toc06 signal-to-noise plus distortion vs. analog input frequency f in (mhz) sinad (db) 100 80 60 40 20 66 67 68 69 70 71 72 65 0120 MAX1438B toc07 total harmonic distortion vs. analog input frequency MAX1438B toc08 f in (mhz) thd (dbc) 100 80 60 40 20 -105 -100 -95 -90 -85 -80 -110 0 120 spurious-free dynamic range vs. analog input frequency MAX1438B toc09 f in (mhz) sfdr (dbc) 100 80 20 40 60 70 75 80 85 90 95 100 105 65 0120 signal-to-noise ratio vs. analog input power MAX1438B toc10 analog input power (dbfs) snr (db) -5 -10 -25 -20 -15 40 45 50 55 60 65 70 75 35 -30 0 f in = 5.3037109mhz signal-to-noise plus distortion vs. analog input power MAX1438B toc11 analog input power (dbfs) sinad (db) -5 -10 -25 -20 -15 40 45 50 55 60 65 70 75 35 -30 0 f in = 5.3037109mhz total harmonic distortion vs. analog input power MAX1438B toc12 analog input power (dbfs) thd (dbc) -5 -10 -15 -20 -25 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -105 -30 0 f in = 5.3037109mhz
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 7 spurious-free dynamic range vs. analog input power MAX1438B toc13 analog input power (dbfs) sfdr (dbc) -5 -10 -15 -20 -25 65 70 75 80 85 90 95 100 105 60 -30 0 f in = 5.3037109mhz signal-to-noise ratio vs. sampling rate MAX1438B toc14 f clk (mhz) snr (db) 60 55 15 20 25 35 40 45 30 50 67 68 69 70 71 72 73 74 66 10 f in = 5.3037109mhz signal-to-noise plus distortion vs. sampling rate MAX1438B toc15 f clk ( mhz ) sinad (db) 60 55 15 20 25 35 40 45 30 50 67 68 69 70 71 72 73 74 66 10 f in = 5.3037109mhz total harmonic distortion vs. sampling rate MAX1438B toc16 f clk (mhz) thd (dbc) 60 55 50 45 40 35 30 25 20 15 -105 -100 -95 -90 -85 -80 -110 10 f in = 5.3037109mhz spurious-free dynamic range vs. sampling rate MAX1438B toc17 f clk (mhz) sfdr (dbc) 60 55 50 45 40 35 30 25 20 15 90 95 100 105 110 115 85 10 f in = 5.3037109mhz signal-to-noise ratio vs. duty cycle MAX1438B toc18 duty cycle (%) snr (db) 65 60 55 50 45 40 35 68 69 70 71 72 73 67 30 70 f in = 5.3037109mhz signal-to-noise plus distortion vs. duty cycle MAX1438B toc19 sinad (db) 65 60 55 50 duty cycle ( % ) 45 40 35 68 69 70 71 72 73 67 30 70 f in = 5.3037109mhz total harmonic distortion vs. duty cycle MAX1438B toc20 thd (dbc) 65 60 55 50 45 40 35 duty cycle (%) -105 -100 -95 -90 -85 -80 -110 30 70 f in = 5.3037109mhz spurious-free dynamic range vs. duty cycle MAX1438B toc21 sfdr (dbc) 65 60 55 50 45 40 35 duty cycle (%) 85 90 95 100 105 110 80 30 70 f in = 5.3037109mhz typical operating characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 64mhz (50% duty cycle), dt = 0, c load = 10pf, t a = +25c, unless otherwise noted.)
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 64mhz (50% duty cycle), dt = 0, c load = 10pf, t a = +25c, unless otherwise noted.) signal-to-noise ratio vs . temperature te m perature ( c) snr (db) -15 10 60 35 68 70 69 67 66 72 71 73 65 -40 85 m ax1438b toc22 f in = 19 . 8 m hz 4096-point data record signal-to-noise plus distortion vs . temperature te m perature ( c) sinad (db) -15 10 60 35 68 70 69 67 66 72 71 73 65 -40 85 m ax1438b toc23 f in = 19 . 8 m hz 4096-point data record total harmonic distortion vs . temperature te m perature ( c) thd (dbc) -15 10 60 35 -90 -88 -89 -91 -94 -92 -93 -86 -87 -85 -95 -40 85 m ax1438b toc24 f in = 19 . 8 m hz 4096-point data record spurious-free dynamic range vs . temperature te m perature ( c) sfdr (dbc) -15 10 60 35 90 92 91 89 86 88 87 94 93 95 85 -40 85 m ax1438b toc25 f in = 19 . 8 m hz 4096-point data record supply current vs. sampling rate (avdd) MAX1438B toc26 f clk (mhz) i avdd (ma) 60 55 5 10 15 25 30 35 40 45 20 50 370 380 390 400 410 420 430 440 360 0 supply current vs. sampling rate (ovdd) MAX1438B toc27 f clk (mhz) i ovdd (ma) 60 55 50 45 40 35 30 25 20 15 10 5 70 75 80 85 90 65 0 offset error vs. temperature MAX1438B toc28 temperature (?c) offset error (%fs) 60 35 10 -15 0.00 0.01 0.02 0.03 -0.01 -40 85 gain error vs. temperature MAX1438B toc29 temperature ( n c) gain error (%fs) 60 35 10 -15 -0.8 -0.6 -0.4 -0.2 0.0 0.2 -1.0 -40 85 integral nonlinearity vs . digital output code m ax1438b toc30 digital output code inl (lsb) 1024 3072 2048 512 2560 3584 1536 -0 . 3 0 -0 . 4 0 . 4 -0 . 2 0 . 2 -0 . 1 0 . 3 0 . 1 0 . 5 -0 . 5 04096
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs _______________________________________________________________________________________ 9 differential nonlinearity vs . digital output code m ax1438b toc31 digital output code dnl (lsb) 1024 3072 2048 512 2560 3584 1536 0 4096 -0 . 3 0 -0 . 4 0 . 4 -0 . 2 0 . 2 -0 . 1 0 . 3 0 . 1 0 . 5 -0 . 5 internal reference voltage vs. supply voltage MAX1438B toc32 supply voltage (v) v refio (v) 2.0 1.9 1.8 1.2500 1.2510 1.2520 1.2530 1.2490 1.7 2.1 v avdd = v ovdd internal reference voltage vs. temperature MAX1438B toc33 temperature ( n c) v refio (v) 60 35 10 -15 1.2400 1.2500 1.2600 1.2700 1.2300 -40 85 v avdd = v ovdd internal reference voltage vs. reference load current i refio ( f a) v refio (v) 250 150 50 -50 -150 -250 1.1500 1.2000 1.2500 1.3000 1.3500 1.4000 1.1000 -350 350 MAX1438B toc34 v avdd = v ovdd cmout voltage vs. supply voltage MAX1438B toc35 supply voltage (v) v cmout (v) 2.0 1.9 1.8 0.7730 0.7750 0.7770 0.7790 0.7810 0.7710 1.7 2.1 v avdd = v ovdd cmout voltage vs. temperature MAX1438B toc36 temperature ( n c) v cmout (v) 60 35 10 -15 0.775 0.780 0.785 0.790 0.795 0.800 0.770 -40 85 v avdd = v ovdd cmout voltage vs. load current i cmout ( f a) v cmout (v) 1500 1000 500 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0 2000 MAX1438B toc37 typical operating characteristics (continued) (v avdd = 1.8v, v ovdd = 1.8v, v cvdd = 1.8v, v gnd = 0v, internal reference, differential input at -0.5dbfs, f in = 5.3mhz, f clk = 64mhz (50% duty cycle), dt = 0, c load = 10pf, t a = +25c, unless otherwise noted.)
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 10 ______________________________________________________________________________________ pin name function 1 in1p channel 1 positive input 2 in1n channel 1 negative input 3 in2p channel 2 positive input 4 in2n channel 2 negative input 5 in3p channel 3 positive input 6 in3n channel 3 negative input 7, 8, 10, 11, 25, 26, 27, 60 avdd analog power input. connect avdd to a 1.7v to 1.9v power supply. bypass avdd to gnd with a 0.1f capacitor as close as possible to the device. bypass the avdd power plane to the gnd plane with a bulk capacitor of at least 2.2f. connect all avdd pins to the same potential. 9, 18, 68 gnd ground. connect all gnd pins to the same potential. 12 in4p channel 4 positive input 13 in4n channel 4 negative input 14 in5p channel 5 positive input 15 in5n channel 5 negative input 16 in6p channel 6 positive input 17 in6n channel 6 negative input 19 in7p channel 7 positive input 20 in7n channel 7 negative input 21 dt double termination select. force dt high to select the internal 100 ? termination between the differential output pairs. force dt low to select no internal output termination. 22 slvs/ lvds differential output signal format select input. force slvs/ lvds high to select slvs outputs. force slvs/ lvds low to select lvds outputs. 23 cvdd clock power input. connect cvdd to a 1.7v to 3.5v supply. bypass cvdd to gnd with a 0.1f capacitor in parallel with a capacitor of at least 2.2f. install the bypass capacitors as close as possible to the device. cvdd is used to bias esd-protection diodes on clk (see figure 2). 24 clk single-ended cmos clock input 28, 31, 34, 39, 44, 49, 52 ovdd output driver power input. connect ovdd to a 1.7v to 1.9v power supply. bypass ovdd to gnd with a 0.1f capacitor as close as possible to the device. bypass the ovdd power plane to the gnd plane with a bulk capacitor of at least 2.2f. connect all ovdd pins to the same potential. 29 out7n channel 7 negative lvds/slvs output 30 out7p channel 7 positive lvds/slvs output 32 out6n channel 6 negative lvds/slvs output 33 out6p channel 6 positive lvds/slvs output 35 out5n channel 5 negative lvds/slvs output 36 out5p channel 5 positive lvds/slvs output 37 out4n channel 4 negative lvds/slvs output 38 out4p channel 4 positive lvds/slvs output 40 framen negative frame-alignment lvds/slvs output. a rising edge on the differential frame output aligns to a valid d0 in the output data stream. 41 framep positive frame-alignment lvds/slvs output. a rising edge on the differential frame output aligns to a valid d0 in the output data stream. 42 clkoutn negative lvds/slvs serial clock output pin description
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 11 pin name function 43 clkoutp positive lvds/slvs serial-clock output 45 out3n channel 3 negative lvds/slvs output 46 out3p channel 3 positive lvds/slvs output 47 out2n channel 2 negative lvds/slvs output 48 out2p channel 2 positive lvds/slvs output 50 out1n channel 1 negative lvds/slvs output 51 out1p channel 1 positive lvds/slvs output 53 out0n channel 0 negative lvds/slvs output 54 out0p channel 0 positive lvds/slvs output 55 lvdstest lvds test pattern enable. force lvdstest high to enable the output test pattern, 0000 1011 1101. as with the analog conversion results, the test pattern data are output lsb first. force lvdstest low for normal operation. 56 stby standby input. force stby high to put the MAX1438B into standby mode. in standby, the reference circuitry remains active. force stby low for normal operation. 57 pll3 pll control input 3. see table 1 for details. 58 pll2 pll control input 2. see table 1 for details. 59 pll1 pll control input 1. see table 1 for details. 61 refn negative reference bypass output. connect a capacitor of at least 1f (10f typ) between refp and refn, and connect a capacitor of at least 1f (10f typ) between refn and gnd. place the capacitors as close as possible to the device on the same side of the pcb as the MAX1438B. 62 refp positive reference bypass output. connect a capacitor of at least 1f (10f typ) between refp and refn, and connect a capacitor of at least 1f (10f typical) between refn and gnd. place the capacitors as close as possible to the device on the same side of the pcb as the MAX1438B. 63 refio reference input/output. for internal reference operation (refadj = gnd), the reference output voltage is 1.24v. for external reference operation (refadj = avdd), apply a stable reference voltage at refio. bypass to gnd with a capacitor of at least 0.1f. 64 refadj internal/external reference mode select and reference adjust input. for internal reference, connect refadj to gnd. for external reference, connect refadj to avdd. for adjusting the reference, see the full-scale range adjustments using the internal reference section. 65 cmout common-mode reference voltage output. cmout outputs the input common-mode voltage for dc-coupled applications. bypass cmout to gnd with a capacitor of at least 0.1f. 66 in0p channel 0 positive input 67 in0n channel 0 negative input ep exposed pad. internally connected to gnd. connect ep to a large ground plane for maximum thermal performance. must be connected to gnd. pin description (continued)
MAX1438B detailed description the MAX1438B adc features fully differential inputs, a pipelined architecture, and digital error correction for high-speed signal conversion. the adc pipeline archi- tecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. the convert- ed digital results are serialized and sent through the lvds/slvs output drivers. the total clock-cycle latency from input to output is 6.5 clock cycles. the MAX1438B offers 8 separate fully differential chan- nels with synchronized inputs and outputs. global standby minimizes power consumption. input circuit figure 1 displays a simplified diagram of the input t/h circuits. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the operational transconduc- tance amplifier (ota), and open simultaneously with s1, sampling the input waveform. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting differ- ential voltages are held on capacitors c2a and c2b. the amplifiers charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these values are octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 12 ______________________________________________________________________________________ MAX1438B lvds/slvs output drivers pll 6x clock circuitry reference syste m in0p in0n in1p in1n in7p in7n clk refadj refio refp refn out0p out0n out1p out1n out7p out7n ovdd avdd gnd cvdd pll3 pll1 pll2 lvdstest dt output control t/h 12-bit pipeline adc 12:1 serializer t/h 12-bit pipeline adc 12:1 serializer fra m ep fra m en clkoutp clkoutn t/h 12-bit pipeline adc 12:1 serializer power control stby slvs/lvds *ic m v = input co mm on- m ode voltage (internally generated) . c m out ic m v* functional diagram
then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. analog inputs, in_p to in_n, are driven differentially. for differ- ential inputs, balance the input impedance of in_p and in_n for optimum performance. reference configurations (refio, refadj, refp, and refn) the MAX1438B provides an internal 1.24v bandgap reference or can be driven with an external reference voltage. the full-scale analog differential input range is fsr. fsr (full-scale range) is given by the following equation: where v refio is the voltage at refio, generated inter- nally or externally. for a v refio = 1.24v, the full-scale input range is 700mv (1.4v p-p ). internal reference mode connect refadj to gnd to use the internal bandgap reference directly. the internal bandgap reference gen- erates v refio to be 1.24v with a 120ppm/c tempera- ture coefficient in internal reference mode. connect an external 0.1f bypass capacitor from refio to gnd for stability. refio sources up to 200a and sinks up to 200a for external circuits, and refio has a 75mv/ma load regulation. putting the MAX1438B into standby mode turns off all circuitry except the reference circuit, allowing the converter to power up faster when the adc exits standby with a high-to-low transitional signal on stby. the internal circuits of the MAX1438B require 200s to power up and settle when the converter exits standby mode. to compensate for gain errors or to decrease or increase the adcs fsr, add an external resistor between refadj and gnd or refadj and refio. this adjusts the internal reference value of the MAX1438B by up to 5% of its nominal value. see the full-scale range adjustments using the internal reference section. fsr v v refio = (. ) . 0 700 124 MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________________________ 13 MAX1438B in_p in_n ota avdd gnd c2a s4b s4c s1 c2b s4a c1a s2a s5a s3a s3b s5b c1b s2b internal bias* out internally generated co mm on- m ode level* switches shown in track m ode internally generated co mm on- m ode level* internal co mm on- m ode bias* internal co mm on- m ode bias* *not externally accessible . internal bias * out figure 1. internal input circuit
MAX1438B connect 1f (10f typ) capacitors to gnd from refp and refn and a 1f (10f typ) capacitor between refp and refn as close as possible to the device on the same side of the pcb. external reference mode the external reference mode allows for more control over the MAX1438B reference voltage and allows multi- ple converters to use a common reference. connect refadj to avdd to disable the internal reference. apply a stable 1.18v to 1.30v source at refio. bypass refio to gnd with a 0.1f capacitor. the refio input impedance is > 1m ? . clock input (clk) the MAX1438B accepts a cmos-compatible clock sig- nal with a wide 20% to 80% input clock duty cycle. drive clk with an external single-ended clock signal. figure 2 shows the simplified clock input diagram. low clock jitter is required for the specified snr perfor- mance of the MAX1438B. analog input sampling occurs on the rising edge of clk, requiring this edge to provide the lowest possible jitter. jitter limits the maxi- mum snr performance of any adc according to the following relationship: where f in represents the analog input frequency and t j is the total system clock jitter. pll inputs (pll1, pll2, pll3) the MAX1438B features a pll that generates an output clock signal with six times the frequency of the input clock. the output clock signal is used to clock data out of the MAX1438B (see the system timing requirements section). set the pll1, pll2, and pll3 pins according to the input clock range provided in table 1. system timing requirements figure 3 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data output. the differential analog input (in_p and in_n) is sampled on the rising edge of the clk signal and the resulting data appears at the digital outputs 6.5 clock cycles later. figure 4 provides a detailed, two-conversion timing diagram of the rela- tionship between the inputs and the outputs. clock output (clkoutp, clkoutn) the MAX1438B provides a differential clock output that consists of clkoutp and clkoutn. as shown in figure 4, the serial output data is clocked out of the MAX1438B on both edges of the clock output. the frequency of the output clock is six times the frequency of clk. frame-alignment output (framep, framen) the MAX1438B provides a differential frame-alignment signal that consists of framep and framen. as shown in figure 4, the rising edge of the frame-align- ment signal corresponds to the first bit (d0) of the 12-bit serial data stream. the frequency of the frame- alignment signal is identical to the frequency of the input clock. serial output data (out_p, out_n) the MAX1438B provides its conversion results through individual differential outputs consisting of out_p and out_n. the results are valid 6.5 input clock cycles after the sample is taken. as shown in figure 3, the out- put data is clocked out on both edges of the output clock, lsb (d0) first. figure 5 provides the detailed ser- ial-output timing diagram. snr ft in j = ? ? ? ? ? ? 20 1 2 log octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 14 ______________________________________________________________________________________ MAX1438B duty-cycle equalizer avdd cvdd clk gnd figure 2. clock input circuitry input clock range (mhz) pll1 pll2 pll3 min max 0 0 0 45.0 64.0 0 0 1 32.5 45.0 0 1 0 22.5 32.5 0 1 1 16.3 22.5 1 0 0 11.3 16.3 1 0 1 8.1 11.3 1 1 0 5.6 8.1 1 1 1 4.0 5.6 table 1. pll1, pll2, and pll3 configuration table
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 15 output data for sa m ple n - 6 output data for sa m ple n *duty cycle varies depending on input clock frequency . clk n n + 2 n + 1 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 6 . 5 clock-cycle data latency t sa m ple (v in_p - v in_n ) (v fra m ep - v fra m en )* (v clkoutp - v clkoutn ) (v out_p - v out_n ) figure 3. global timing diagram n n + 2 n + 1 *duty cycle depends on input clock frequency . t cf (v in_p - v in_n ) clk (v fra m ep - v fra m en )* (v clkoutp - v clkoutn ) (v out_p - v out_n ) d5 n-7 d6 n-7 d7 n-7 d8 n-7 d9 n-7 d10 n-7 d11 n-7 d0 n-6 d1 n-6 d2 n-6 d3 n-6 d4 n-6 d5 n-6 d6 n-6 d7 n-6 d8 n-6 d9 n-6 d10 n-6 d11 n-6 d0 n-5 d1 n-5 d2 n-5 d3 n-5 d4 n-5 d5 n-5 d6 n-5 t sa m ple t sf figure 4. detailed two-conversion timing diagram (v clkoutp - v clkoutn ) (v out_p - v out_n ) t ch t cl t od t od d0 d1 d2 d3 figure 5. serialized-output detailed timing diagram
MAX1438B output data transfer function the MAX1438B output data format is twos comple- ment. the following equation, table 2, and figure 6 define the relationship between the digital output and the analog input: where code 10 is the decimal equivalent of the digital output code as shown in table 2. keep the capacitive load on the MAX1438B digital out- puts as low as possible. lvds and slvs selection (slvs/ lvds ) drive slvs/ lvds low for lvds or drive slvs/ lvds high for slvs levels at the MAX1438B outputs (out_p, out_n, clkoutp, clkoutn, framep, and framen). for slvs levels, enable double-termination by driving dt high. see the electrical characteristics table for lvds and slvs output voltage levels. vvfsr code in p in n __ ? = 2 4096 10 octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 16 ______________________________________________________________________________________ two?-complement digital output code binary d11 d0 hexadecimal equivalent of d11 d0 decimal equivalent of d11 d0 v in _ p - v in _ n (mv) (v refio = 1.24v) 0111 1111 1111 0x7ff +2047 +699.66 0111 1111 1110 0x7fe +2046 +699.32 0000 0000 0001 0x001 +1 +0.34 0000 0000 0000 0x000 0 0 1111 1111 1111 0xfff -1 -0.34 1000 0000 0001 0x801 -2047 -699.66 1000 0000 0000 0x800 -2048 -700.00 table 2. output code table (v refio = 1.24v) differential input voltage (lsb) -2045 +2047 +2045 -1 0 +1 -2047 0x800 0x801 0x802 0x803 0x7ff 0x7fe 0x7fd 0xfff 0x000 0x001 fsr fsr 1 lsb = 2 x fsr 4096 fsr = 700mv x v refio 1 . 24v two's-co m ple m ent output code (lsb) figure 6. twos-complement transfer function
lvds test pattern (lvdstest) drive lvdstest high to enable the output test pattern on all lvds or slvs output channels. the output test pattern is 0000 1011 1101. drive lvdstest low for nor- mal operation (test pattern disabled). common-mode output (cmout) cmout provides a common-mode reference for dc- coupled analog inputs. if the input is dc-coupled, match the output common-mode voltage of the circuit driving the MAX1438B to the output voltage at v cmout to within 50mv. it is recommended that the output common-mode voltage of the driving circuit be derived from cmout. double termination (dt) the MAX1438B offers an optional, internal 100 ? termi- nation between the differential output pairs (out_p and out_n, clkoutp and clkoutn, framep and framen). in addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflections down the line. this feature is useful in applications where trace lengths are long (> 5in) or with mismatched impedance. drive dt high to select double-termination, or drive dt low to disconnect the internal termination resistor (single-ter- mination). selecting double-termination increases the ovdd supply current (see figure 7). standby mode the MAX1438B offers a standby mode to efficiently use power by transitioning to a low-power state when con- versions are not required. stby controls the standby mode of all channels and the internal reference circuitry. the reference does not power down in standby mode. drive stby high to enable standby. in standby mode, the output impedance of all of the lvds/slvs outputs is approximately 342 ? , if dt is low. the output impedance of the differential lvds/slvs outputs is 100 ? when dt is high. see the electrical characteristics table for typi- cal supply currents during standby. the following list shows the state of the analog inputs and digital outputs in standby mode: ? in_p, in_n analog inputs are disconnected from the internal input amplifier. ? reference circuit remains active. ? out_p, out_n, clkoutp, clkoutn, framep, and framen have approximately 342 ? between the output pairs when dt is low. when dt is high, the dif- ferential output pairs have 100 ? between each pair. when operating in internal reference mode, the MAX1438B requires 200s to power up and settle when the converter exits standby mode. to exit standby mode, stby, the applied control signal must transition from high to low. when using an external reference, the wake- up time is dependent on the external reference drivers. applications information full-scale range adjustments using the internal reference the MAX1438B supports a full-scale adjustment range of 10% (5%). to decrease the full-scale range, add a 25k ? to 250k ? external resistor or potentiometer (r adj ) between refadj and gnd. to increase the full-scale range, add a 25k ? to 250k ? resistor between refadj and refio. figure 8 shows the two possible configurations. the following equations provide the relationship between r adj and the change in the analog full-scale range: for r adj connected between refadj and refio, and: for r adj connected between refadj and gnd. fsr v k r adj = ? ? ? ? ? ? ? 07 1 125 . . ? fsr v k r adj =+ ? ? ? ? ? ? 07 1 125 . . ? MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________________________ 17 MAX1438B 100 ? 100 ? out_p/ clkoutp/ fra m ep out_n/ clkoutn/ fra m en dt switches are closed when dt is high . switches are open when dt is low . z 0 = 50 ? z 0 = 50 ? figure 7. double termination
MAX1438B using transformer coupling an rf transformer (figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal. the MAX1438B input com- mon-mode voltage is internally biased to 0.76v (typ) with f clk = 64mhz. although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. grounding, bypassing, and board layout the MAX1438B requires high-speed board layout design techniques. refer to the MAX1438B ev kit data sheet for a board layout reference. locate all bypass capacitors as close as possible to the device, prefer- ably on the same side as the adc, using surface-mount devices for minimum inductance. bypass avdd to gnd with a 0.1f ceramic capacitor in parallel with a 0.1f ceramic capacitor. bypass ovdd to gnd with a 0.1f ceramic capacitor in parallel with a 2.2f ceramic capacitor. bypass cvdd to gnd with a 0.1f ceramic capacitor in parallel with a 2.2f ceramic capacitor. multilayer boards with ample ground and power planes produce the highest level of signal integrity. connect the MAX1438B ground pins and the exposed backside pad to the same ground plane. the MAX1438B relies on the exposed-backside-pad connection for a low- inductance ground connection. isolate the ground plane from any noisy digital system ground planes. route high-speed digital signal traces away from the sensitive analog traces. keep all signal lines short and free of 90 turns. ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equal- ly. refer to the MAX1438B ev kit data sheet for an example of symmetric input layout. parameter definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. for the MAX1438B, this straight line is between the end points of the transfer function, once offset and gain errors have been nulli- fied. inl deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics table. differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. for the MAX1438B, dnl deviations are measured at every step and the worst- case deviation is reported in the electrical characteristics table. octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 18 ______________________________________________________________________________________ reference buffer refio refadj av cc av cc /2 control line to disable reference buffer adc full-scale = reft - refb g 1v 0 . 1 f reference- scaling a m plifier reft refb 25k ? to 250k ? 25k ? to 250k ? MAX1438B figure 8. circuit suggestions to adjust the adcs full-scale range MAX1438B v in 0 . 1 f 0 . 1 f n . c . 1 2 3 6 5 4 t1 m inicircuits adt1-1wt 10 ? 10 ? 39pf 39pf in_p in_n figure 9. transformer-coupled input drive
offset error offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. for the MAX1438B, the ideal midscale digital output transition occurs when there is -1/2 lsbs across the analog inputs (figure 6). bipolar offset error is the amount of deviation between the mea- sured midscale transition point and the ideal midscale transition point. gain error gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. for the MAX1438B, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. for the bipolar device (MAX1438B), the full-scale transi- tion point is from 0x7fe to 0x7ff and the zero-scale transition point is from 0x800 to 0x801. crosstalk crosstalk indicates how well each analog input is isolated from the others. for the MAX1438B, a 5.3mhz, -0.5dbfs analog signal is applied to 1 channel while a 30.3mhz, -0.5dbfs analog signal is applied to another channel. an fft is taken on the channel with the 5.3mhz analog signal. from this fft, the crosstalk is measured as the difference in the 5.3mhz and 30.3mhz amplitudes. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. see figure 10. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the aperture delay. see figure 10. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adcs reso- lution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, there are other noise sources besides quantiza- tion noise: thermal noise, reference noise, clock jitter, etc. for the MAX1438B, snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist fre- quency excluding the fundamental, the first six harmon- ics (hd2Chd7), and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms signal to the rms noise plus distortion. rms noise plus distor- tion includes all spectral components to the nyquist fre- quency, excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmon- ics of the input signal to the fundamental itself. this is expressed as: spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. sfdr is specified in decibels relative to the carrier (dbc). thd vvvvvv v = +++++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 log enob sinad = ? ? ? ? ? ? ? 176 602 . . MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs ______________________________________________________________________________________ 19 clk analog input sa m pled data t/h t ad hold track hold t aj figure 10. aperture jitter/delay specifications
MAX1438B intermodulation distortion (imd) imd is the total power of the im2 to im5 intermodulation products to the nyquist frequency relative to the total input power of the two input tones, f 1 and f 2 . the indi- vidual input tone levels are at -6.5dbfs. the intermodu- lation products are as follows: ? 2nd-order intermodulation products (im2): f 1 + f 2 , f 2 - f 1 ? 3rd-order intermodulation products (im3): 2 x f 1 - f 2 , 2 x f 2 - f 1 , 2 x f 1 + f 2 , 2 x f 2 + f 1 ? 4th-order intermodulation products (im4): 3 x f 1 - f 2 , 3 x f 2 - f 1 , 3 x f 1 + f 2 , 3 x f 2 + f 1 ? 5th-order intermodulation products (im5): 3 x f 1 - 2 x f 2 , 3 x f 2 - 2 x f 1 , 3 x f 1 + 2 x f 2 , 3 x f 2 + 2 x f 1 third-order intermodulation (im3) im3 is the total power of the 3rd-order intermodulation product to the nyquist frequency relative to the total input power of the two input tones, f 1 and f 2 . the indi- vidual input tone levels are at -6.5dbfs. the 3rd-order intermodulation products are 2 x f 1 - f 2 , 2 x f 2 - f 1 , 2 x f 1 + f 2 , 2 x f 2 + f 1 . small-signal bandwidth a small -20.5dbfs analog input signal is applied to an adc so that the signals slew rate does not limit the adcs performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. gain matching gain matching is a figure of merit that indicates how well the gain of all 8 adc channels is matched to each other. for the MAX1438B, gain matching is measured by applying the same 5.3mhz, -0.5dbfs analog signal to all analog input channels. these analog inputs are sampled at 64msps and the maximum deviation in amplitude is reported in db as gain matching in the electrical characteristics table. phase matching phase matching is a figure of merit that indicates how well the phases of all 8 adc channels are matched to each other. for the MAX1438B, phase matching is measured by applying the same 5.3mhz, -0.5dbfs analog signal to all analog input channels. these ana- log inputs are sampled at 64msps and the maximum deviation in phase is reported in degrees as phase matching in the electrical characteristics table. octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs 20 ______________________________________________________________________________________
MAX1438B octal, 12-bit, 64msps, 1.8v adc with serial lvds outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. out1p out1n ovdd out2n out2p out3p ovdd fra m ep fra m en clkoutp clkoutn out3n ovdd out5p out5n out4p out4n in2p in2n in3p avdd avdd gnd in1n in1p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 67 68 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 slvs/lvds cvdd clk avdd dt in7n in7p gnd in0n in0p c m out refadj refio refp refn avdd pll1 pll2 pll3 stby lvdstest out0n gnd m ax1438b top view in3n avdd in4p in4n in5n in6p in6n avdd in5p out7p ovdd out6n ovdd out7n ovdd avdd out6p tqfn (10mm x 10mm x 0.8mm) + avdd out0p ovdd exposed pad . connected to gnd . pin configuration package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 68 tqfn-ep t6800-4 21-0142

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